The present invention relates generally to data storage systems for use with computing systems and, more particularly, to techniques for maintaining data on non-volatile memory storage device.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. Typically, a memory controller on a separate integrated circuit chip is provided as an interface to a host. The host can use the controller to perform various operations (e.g., read, write) on the non-volatile memory. A controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stock cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. Besides a memory card implementation, non-volatile memory can alternatively be embedded into various types of host systems.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, either states store three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in the aforementioned U.S. Patent Application Publication No. 2003/0109093. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Memory cells of a typical flash EEPROM array are divided into discrete “blocks” of cells that are erased together. Each erase block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the erase block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each erase block, and each page stores one or just a few host sectors of data. It should also be noted that in order to re-write data to a block, the block should be erased first.
In order to increase the degree to parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, erase blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one erase block from each plane. Use of the metablock is described in International Patent Application Publication No. WO 02/058074. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all erase blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page.
From the perspective of a host application, flash memory can be divided into a logical address space starting from a logical address zero (0) and ending with a logical address N. FIG. 1 illustrates a host's logical address space 102 which is partitioned into “logical sectors”. The host groups several (e.g., four (4)) logical sectors into a cluster. As shown in FIG. 1, a host may divide the logical address space 102 into clusters that include clusters A, B, C, D, E, F, G and H. As such, each of these clusters may represent a predetermined number of sectors (e.g., four (4) logical sectors per cluster). In any case, the host allocates data in a logical unit of data which can be referred to as a “cluster”. For example, clusters A, B and C may be used to allocate a file 1, while cluster D is used to allocate a file 2. It should be noted that the host allocates files in clusters. However, not all the logical sectors in a cluster need to contain data for a file. By way of example, only a portion (e.g., only one logical sector) of cluster C may have data. Nevertheless, the host typically allocates a cluster to a file even though not all the logical sectors in the cluster are needed.
A host can use a File Allocation Table (FAT) 104 to keep track of files. The File Allocation Table (FAT) 104 effectively represents a logical file structure and also indicates what cluster has been allocated for each of the files in the logical file structure. The host maintains the logical file structure by updating the File Allocation Table (FAT) 104. By way of example, when a new file is allocated, the File Allocation Table (FAT) 104 is updated to, among other things, indicate which clusters have been allocated for the new file. Also, when a file or directory is deleted, the host updates the File Allocation Table (FAT) 104. It should be noted that clusters may be deallocated by the host as a result of an update. By way of example, when the host deletes file 1, an updated File Allocation Table (FAT) 106 may result where the host effectively deallocates clusters A, B, and C which were allocated for storing file 1.
In contrast to a host's logical address space, the logical address space of a flash-memory controller is divided into “logical blocks”. In other words, the same logical address space 102 may be represented as a logical address space 103 for the controller. As shown in FIG. 1, the logical address space 103 may be divided into various logical blocks, including logical block 1 and logical block 2. These logical blocks are mapped into physical blocks of memory that can be erased as a unit. For example, logical block 1 may be mapped into physical block 2, and so on. In summary, the host and controller use different logical units of memory. The host divides the logical address space into clusters while the controller divides the logical address space into logical blocks. It should also be noted that typically host clusters are applied to logical address space allocated for application data and sub-directory entries only. In addition, logical address space allocated for other system data may not be managed by the host as clusters. It should also be noted that the first cluster is not normally located at the beginning of the logical address space. Clusters and logical blocks may therefore not align with each other.
A conventional controller, however, is not aware of the logical organization used by the host. Conventionally, the controller simply maps the logical address 102 used by the host to a logical address 103 and then into a physical address 110. This means that a conventional controller does not consider the host's logical organization of data or consequences that a host operation may have had on data. By way of example, when a new file is allocated, the logical file system 104 is updated to, among other things, indicate which clusters have been allocated for the new file. Also, when a file or directory is deleted, the host updates the logical file system 104. Moreover, one or more clusters may be deallocated by a host. By way of example, when the host deletes file 1, the updated File Allocation Table 106 indicates that the host has effectively deallocated clusters A, B, and C which were previously allocated for storing file 1 (i.e., file 1 is no longer represented in updated File Allocation Table 106). Although clusters A, B, and C have been deallocated by the host and can be erased, a conventional controller does not “garbage collect” that data corresponding to deallocated clusters A, B, and C. This means that the data will persist on memory. In addition, the deallocated data may be copied a number of times when blocks are updated during garbage collection when data in two blocks may be combined into one block.
To further illustrate, an original physical block 120 is depicted in FIG. 1. For simplicity, it is assumed that the original physical block 120 includes data corresponding to logical clusters A, B, C and D used by the host to allocate files 1 and 2. Also, further assuming that the host has later deallocated file 1 (clusters A, B and C), the original physical block 120 still contains all the logical clusters A, B, C and D because the controller has no way of knowing that file 1 has been deallocated by the host. The host, however, has requested the controller to update data portion D of the original physical block 120. In other words, at some point the host may want to change file 2, so it sends a write request using the logical address it knows for data corresponding to one or more logical sectors that should be updated. The controller determines that these logical sectors addressed by the host correspond to sectors that already have been written to by the host (i.e., Cluster D), so an update block 122 is used partly because data in original physical block 120 cannot be overwritten. This means that two physical blocks may be used to represent a logical block for some time until the update block 122 is “closed” (i.e., all data in original block 120 is copied to block 122). The original block 120 and the update block 122 may be combined, for example, during a garbage collection cycle, so that the update block 122 becomes an “original” block 122 and the previous original block 120 is erased and returned to a pool of available memory blocks. In any case, it should be noted that data corresponding to the deallocated clusters (A, B, and C) are copied sooner or later to the update block 122 so that update block 122 can be closed and original block 120 can be erased. The controller may maintain a mapping table within volatile memory or non-volatile memory defining the allocation of physical memory blocks to logical blocks of data. Copying data stored in non-volatile memory takes a significant amount of time and resources. However, copying deallocated data (e.g., deallocated clusters A, B, and C) is not necessary. Thus, system performance can be further enhanced if deallocated data is not copied. In general, it is desirable to enhance system performance as much as possible while adhering to the addressing conventions that are widely used.
Accordingly, alternative non-volatile memory management techniques would be useful.